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? semiconductor components industries, llc, 2013 september, 2013 ? rev. 8 1 publication order number: nb6n14s/d nb6n14s 3.3 v 1:4 anylevel differential input to lvds fanout buffer/translator the nb6n14s is a differential 1:4 clock or data receiver and will accept anylevel differential input signals: lvpecl, cml or lvds. these signals will be translated to lvds and four identical copies of clock or data will be distributed, operating up to 2.0 ghz or 2.5 gb/s, respectively. as such, the nb6n14s is ideal for sonet, gige, fiber channel, backplane and other clock or data distribution applications. the nb6n14s has a wide input common mode range from gnd + 50 mv to v cc ? 50 mv. combined with the 50 internal termination resistors at the i nputs, the nb6n14s is ideal for translating a variety of differential or single ? ended clock or data signals to 350 mv typical lvds output levels. the nb6n14s is offered in a small 3 mm x 3 mm 16 ? qfn package. application notes, models, and support documentation are available at www.onsemi.com . the nb6n14s is a member of the eclinps max family of high performance products. features ? maximum input clock frequency > 2.0 ghz ? maximum input data rate > 2.5 gb/s ? 1 ps maximum rms clock jitter ? typically 10 ps data dependent jitter ? 380 ps typical propagation delay ? 120 ps typical rise and fall times ? v ref_ac reference output ? tia/eia ? 644 compliant ? functionally compatible with existing 3.3 v lvel, lvep, ep, and sg devices ? these are pb ? free devices time (58 ps/div) figure 2. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv; input signal ddj = 14 ps) voltage (130 mv/div) device ddj = 10 ps a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information 16 nb6n 14s alyw 1 q3 q3 figure 1. logic diagram q2 q2 q1 q1 q0 q0 en dq (lvttl/cmos) v ref_ac 50 50 in vt /in (note: microdot may be in either location) 1 + r pu
nb6n14s http://onsemi.com 2 figure 3. nb6n14s pinout, 16 ? pin qfn (top view) q3 q3 v cc en gnd in v t v ref_ac in q1 q1 q2 q2 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb6n14s exposed pad (ep) q0 q0 v cc in in en q 01 1 0 10 1 1 x x 0 0 (note 1) 1. on next transition of the input signal (in). table 1. truth table q 1 0 1 (note 1) table 2. pin description pin name i/o description 1 q1 lvds output non ? inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 2 q1 lvds output inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 3 q2 lvds output non ? inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 4 q2 lvds output inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 5 q3 lvds output non ? inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 6 q3 lvds output inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 7 v cc ? positive supply voltage. 8 en lvttl / lvcmos input synchronous output enable. when low, q outputs will go low and qb outputs will go high on the next negative transition of in input. the internal dff register is clocked on the falling edge of in input; see figure 23. the en pin has an internal pullup resistor and defaults high when left open. 9 in lvpecl, cml, lvds inverted differential input 10 v ref_ac lvpecl output the v ref_ac reference output can be used to rebias capacitor ? coupled differential or single ? ended input signals. for the capacitor ? coupled in and/or inb inputs, v ref_ac should be connected to the vt pin and bypassed to ground with a 0.01 f capacitor. 11 v t lvpecl output internal 100 center ? tapped termination pin for in and in 12 in lvpecl, cml, lvds non ? inverted differential input. (note 2) 13 gnd ? negative supply voltage. 14 v cc ? positive supply voltage. 15 q0 lvds output non ? inverted in output. typically loaded with 100 receiver termination resistor across differential pair. 16 q0 lvds output inverted in output. typically loaded with 100 receiver termination resistor across differential pair. ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to gnd on the pc board. 2. in the dif ferential configuration, when the input termination pin (vt) is connected to a termination voltage or left open, and if no sign al is applied on in/in inputs, then the device will be susceptible to self ? oscillation.
nb6n14s http://onsemi.com 3 table 3. attributes characteristics value moisture sensitivity (note 3) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in esd protection human body model machine model > 2 kv > 200 v en input pullup resistor ? r pu 37 k transistor count 225 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.8 v v in positive input gnd = 0 v v in v cc 3.8 v i in input current through r t (50 resistor) static surge 35 70 ma ma i osc output short circuit current line ? to ? line (q to q ) line ? to ? end (q or q to gnd) tia/eia ? 644 compliant q or q q to q to gnd continuous continuous 12 24 ma i ref_ac v ref_ac sink/source current 0.5 ma t a operating temperature range qfn ? 16 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 41.6 35.2 c/w c/w jc thermal resistance (junction ? to ? case) 1s2p (note 4) qfn ? 16 4.0 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 1s2p (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb6n14s http://onsemi.com 4 table 5. dc characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit i cc power supply current (note 9) 65 100 ma differential inputs driven single ? ended (figures 14, 15, 19, and 21) v th input threshold reference voltage range (note 8) gnd +100 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v ref_ac reference output voltage (note 11) v cc ? 1.600 v cc ? 1.425 v cc ? 1.300 v differential inputs driven differentially (figures 10, 11, 12, 13, 20, and 22) v ihd differential input high voltage 100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v cmr input common mode range (differential configuration) gnd + 50 v cc ? 50 mv v id differential input voltage (v ihd ? v ild ) 100 v cc mv r tin internal input termination resistor 40 50 60 lvds outputs (note 5) v od differential output voltage 250 450 mv v od change in magnitude of v od for complementary output states (note 10) 0 1 25 mv v os offset voltage (figure 18) 1125 1375 mv v os change in magnitude of v os for complementary output states (note 10) 0 1 25 mv v oh output high voltage (note 6) 1425 1600 mv v ol output low voltage (note 7) 900 1075 mv lvttl/lvcmos inputs v ih input high voltage (note 7, 8) 2.0 v cc v v il input low voltage (note 7, 8) gnd 0.8 v i ih input high current ? 150 150 a i il input low current ? 150 150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. lvds outputs require 100 receiver termination resistor between differential pair. see figure 17. 6. v oh max = v os max + ? v od max. 7. v ol max = v os min ? ? v od max. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. input termination pins open, d/d at the dc level within v cmr and output pins loaded with r l = 100 across differential. 10. parameter guaranteed by design verification not tested in production. 11. v ref_ac used to rebias capacitor ? coupled inputs only (see figures 14 and 15).
nb6n14s http://onsemi.com 5 table 6. ac characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v; (note 12) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f inmax maximum input clock frequency 2.0 2.0 2.0 ghz v outpp output voltage amplitude (@ v inppmin )f in 1.0 ghz (figure 4) f in = 1.5 ghz f in = 2.0 ghz 220 200 170 350 300 270 220 200 170 350 300 270 220 200 170 350 300 270 mv f data maximum operating data rate 1.5 2.5 1.5 2.5 1.5 2.5 gb/s t plh , t phl differential input to differential output propagation delay 300 450 600 300 450 600 300 450 600 ps t s t h setup time hold time 300 500 60 70 300 500 60 70 300 500 60 70 t skew within device skew (note 17) device ? to ? device skew (note 16) 5 30 20 200 5 30 20 200 5 30 20 200 ps t jitter rms random clock jitter (note 14) f in = 1.0 ghz f in = 1.5 ghz deterministic jitter (note 15) f data = 622 mb/s f data = 1.5 gb/s f data = 2.488 gb/s 0.5 0.5 6.0 7.0 10 1.0 1.0 20 20 20 0.5 0.5 6.0 7.0 10 1.0 1.0 20 20 20 0.5 0.5 6.0 7.0 10 1.0 1.0 20 20 20 ps v inpp input voltage swing/sensitivity (differential configuration) (note 13) 100 v cc ? gnd 100 v cc ? gnd 100 v cc ? gnd mv t r t f output rise/fall times @ 250 mhz q, q (20% ? 80%) 60 120 190 60 120 190 60 120 190 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. measured by forcing v inppmin with 50% duty cycle clock source and v cc ? 1400 mv offset. all loading with an external r l = 100 . input edge rates 150 ps (20% ? 80%). see figure 17. 13. input voltage swing is a single ? ended measurement operating in differential mode. 14. rms jitter with 50% duty cycle clock signal at 750 mhz. 15. deterministic jitter with input nrz data at prbs 2 23 ? 1 and k28.5. 16. skew is measured between outputs under identical transition @ 250 mhz. 17. the worst case condition between q0/q0 and q1/q1 from either d0/d0 or d1/d1 , when both outputs have the same transition. input clock frequency (ghz) figure 4. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature (@ v cc = 3.3 v) output voltage amplitude (mv) 0 50 100 150 200 250 300 350 400 0.5 1 1.5 2 2.5 3 0 85 c ? 40 c 25 c
nb6n14s http://onsemi.com 6 figure 5. typical phase noise plot at f carrier = 156.25 mhz figure 6. typical phase noise plot at f carrier = 622.08 mhz figure 7. typical phase noise plot at f carrier = 1 ghz figure 8. typical phase noise plot at f carrier = 1.5 ghz the above phase noise plots captured using agilent e5052a show additive phase noise of the nb6n14s device at frequencies 156.25 mhz, 622.08 mhz, 1 ghz and 1.5 ghz respectively at an operating voltage of 3.3 v in room temperature. the rms phase jitter contributed by the device (integrated between 12 khz and 20 mhz; as shown in the shaded region of the plot) at each of the frequencies is 182 fs, 31 fs, 20 fs and 15 fs respectively . the input source used for the phase noise measurements is agilent e8663b.
nb6n14s http://onsemi.com 7 time (58 ps/div) figure 9. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 and oc48 mask (v inpp = 100 mv; input signal ddj = 14 ps) voltage (63.23 mv/div) device ddj = 10 ps
nb6n14s http://onsemi.com 8 v cc lvpecl driver clk 50 z o = 50 z o = 50 50 clk nb6n14s v cc v cc cml driver clk 50 z o = 50 z o = 50 50 clk v cc v t = v cc figure 10. lvpecl interface figure 11. lvds interface v t = v cc ? 2.0 v figure 12. standard 50 load cml interface v cc lvds driver clk 50 z o = 50 z o = 50 50 clk v cc v t = open v cc hstl driver clk 50 z o = 50 z o = 50 50 clk v cc v t =v ee figure 13. standard 50 load hstl interface v ee v ee v ee v ee v ee v ee v ee v ee v cc differential driver clk 50 z o = 50 z o = 50 50 clk v cc v t = v ref_ac figure 14. capacitor ? coupled differential interface (v t connected to v ref _ ac ) v cc single ? ended driver clk 50 z o = 50 50 clk v cc v ee v ee v ee v ee figure 15. capacitor ? coupled single ? ended interface (v t connected to v ref _ ac ) nb6n14s nb6n14s nb6n14s nb6n14s nb6n14s v t = v ref_ac
nb6n14s http://onsemi.com 9 figure 16. ac reference measurement d d q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) figure 17. typical lvds termination for output driver and device evaluation driver device oscilloscope qd q d lvds 100 z o = 50 z o = 50 hi z probe hi z probe v ol q n v oh q n v os v od figure 18. lvds output figure 19. differential input driven single ? ended in figure 20. differential inputs driven differentially in v th v th in in v ih v il v ihmax v ilmax v ihmin v ilmin v cc v thmax v thmin gnd v th figure 21. v th diagram in in v il v ih(max) v ih v il v ih v il(min) v cmr gnd figure 22. v cmr diagram v inpp = v ihd ? v ild v cc
nb6n14s http://onsemi.com 10 v inpp /in in v cc /2 t s v cc /2 t h t pd en /q q v outpp figure 23. en timing diagram ordering information device package shipping ? nb6n14smng qfn ? 16, 3 x 3 mm (pb ? free) 123 units / rail nb6n14smnr2g qfn ? 16, 3 x 3 mm (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb6n14s http://onsemi.com 11 package dimensions qfn16 3x3, 0.5p case 485g issue f *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package soldering footprint* ??? ??? ??? 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x l1 detail a l alternate terminal constructions ?? 0.10 c a b e/2 dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.03 0.05 a3 0.20 ref b 0.18 0.24 0.30 d 3.00 bsc d2 1.65 1.75 1.85 e 3.00 bsc e2 1.65 1.75 1.85 e 0.50 bsc k 0.18 typ l 0.30 0.40 0.50 l1 0.00 0.08 0.15 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb6n14s/d anylevel and eclinps max are trademarks of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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